Freescale Semiconductor /MKL28T7_CORE1 /SEMA421 /RSTGT_R

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Interpret as RSTGT_R

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RSTGTN0RSTGMS0 (00)RSTGSM 0ROZ

RSTGSM=00

Description

Reset Gate Read

Fields

RSTGTN

Reset Gate Number

RSTGMS

Reset Gate Bus Master

RSTGSM

Reset Gate Finite State Machine

0 (00): Idle, waiting for the first data pattern write.

1 (01): Waiting for the second data pattern write.

2 (10): The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The “01” state persists for only one clock cycle. Software cannot observe this state.

3 (11): This state encoding is never used and therefore reserved.

ROZ

This field always returns the value 0 when read.

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